Bipolar-CMOS-DMOS (BCD, where CMOS stands for “complementary metal-on-semiconductor” and DMOS stands for “double-diffused metal-on-semiconductor”) and triple well process have been widely used in high-voltage (HV) applications, such as electrostatic discharge (ESD) protection. Generally, the ESD performance of an HV ESD protection device depends on total width of gates of the device, as well as surface or lateral rules of the device. For an HV ESD protection device of smaller size, the surface-bulk ratio is larger as compared to a device of larger size, and thus the surface area of the device of smaller size has a larger impact on device performance as compared to that of the device of larger size. As a result, obtaining good ESD performance in devices having relatively small sizes is more challenging. Further, as the operation voltage of a device increases, on-chip ESD protection design also becomes more challenging.
An HV ESD protection device typically has a low on-state resistance (RDS-on). When ESD occurs, the ESD current is more likely to concentrate near the surface or the drain of the HV protection device. This results in a higher current density and electric field at surface junction regions, and results in physical damage to these regions during an ESD event. As a result, the surface area of the HV protection device may have a larger impact on its performance as compared to a device having a larger on-state resistance, and thus surface or lateral rules play a more important role in the HV protection device.
Other characteristics of an HV protection device include, for example, a high breakdown voltage, which is always higher than an operation voltage of the HV protection device. Further, a trigger voltage (Vt1) of the HV device is often much higher than the breakdown voltage of the HV device. Therefore, during an ESD event, the device or internal circuit being protected (also referred to herein as the “protected device/circuit”) may face the risk of being damaged before the HV protection device ever turns on to provide ESD protection. Conventionally, to reduce the trigger voltage of the HV protection device, an additional external ESD detection circuit may be needed.
The HV protection device usually has a low holding voltage, which may result in the HV protection device being triggered by unwanted noise, a power-on peak voltage, or a surge voltage. As a result, latch-up may occur during normal operation.
Further, there may be a field plate effect in the HV protection device. That is, an electric field distribution in the HV protection device is sensitive to routing of wirings that connect different elements or different portions of a device. As a result, the ESD current is more likely to concentrate near the surface or the drain of the HV device.